The present disclosure relates to semiconductor devices and methods for fabricating the semiconductor devices, and specifically relates to semiconductor devices which include a metal-insulator-semiconductor field-effect transistor (MISFET) including a gate insulating film having a high dielectric constant film (a high-k film) containing a metal for adjustment, and methods for fabricating the semiconductor devices.
In recent years, for the purpose of lower power consumption and higher speed of a semiconductor integrated circuit device, a semiconductor device has been proposed which includes a MISFET (hereinafter referred to as a “MIS transistor”) including a high-k film (e.g., a hafnium (Hf)-based film etc.) as the gate insulating film, and a metal film, or a metal film and a silicon film, as the gate electrode.
An n-type MIS transistor has been proposed which includes a Hf-based film containing, for example, lanthanum (La) as the gate insulating film to reduce a threshold voltage (see, for example, Japanese Patent Publication No. 2009-194352).
The reason why the threshold voltage of the n-type MIS transistor can be reduced by employing the Hf-based film containing La as the gate insulating film is as follows. That is, if the Hf-based film contains La, dipoles are generated in the Hf-based film. As a result, a flat-band voltage is shifted toward a negative region, so that the effective work function of the n-type MIS transistor is shifted toward the band edge, and therefore, the threshold voltage of the n-type MIS transistor can be reduced.
A configuration of a conventional semiconductor device will be described below with reference to FIG. 14 and FIGS. 15A-15B. The conventional semiconductor device is a semiconductor device including an n-type MIS transistor which includes a gate insulating film including a high-k film containing La. FIG. 14 is a plan view showing a configuration of the conventional semiconductor device. FIG. 15A is a cross-sectional view showing the configuration of the conventional semiconductor device taken along the gate length direction. FIG. 15B is a cross-sectional view showing the configuration of the conventional semiconductor device taken along the gate width direction. Specifically, FIG. 15A and FIG. 15B are the cross-sectional views taken along the line XVa-XVa and the line XVb-XVb in FIG. 14, respectively.
As shown in FIG. 14 and FIGS. 15A-15B, the conventional semiconductor device includes an n-type MIS transistor nTr. A p-type well region 102 is formed in a semiconductor substrate 100.
As shown in FIGS. 15A-15B, the n-type MIS transistor nTr includes a gate insulating film 103A formed on an active region 100a surrounded by an isolation region 101, a gate electrode 105A formed on the gate insulating film 103A, n-type extension regions 106 formed in the active region 100a laterally outside the gate electrode 105A (see, in particular, FIG. 15A), a sidewall 108A formed on a side surface of the gate electrode 105A, and n-type source/drain regions 109 formed in the active region 100a laterally outside the sidewall 108A (see, in particular, FIG. 15A).
As shown in FIG. 14, the gate electrode 105A is formed on the active region 100a surrounded by the isolation region 101, with the gate insulating film (see 103A in FIGS. 15A and 15B) interposed between the gate electrode 105A and the active region 100a. The sidewall 108A is formed on the side surface of the gate electrode 105A.
The gate insulating film 103A includes a high-k film 103 containing La. The gate electrode 105A includes a metal film 104 and a silicon film 105. The sidewall 108A includes an inner sidewall 107 and an outer sidewall 108.